| 摘要 |
A non-volatile, multi-bit-per-cell memory has a read circuit that includes a counter, a row line driver, and a sense circuit. During a read, the driver changes a read signal applied to the control gate of a selected memory cell being read. The counter simultaneously counts cycles of a clock signal. When the sense circuit sense a change in conductivity of the selected memory cell, the count in the counter indicates a multi-bit digital value corresponding to the threshold voltage of the selected memory cell and can be used to generate an output data signal. In one embodiment, the driver includes a digital-to-analog converter that generates the read signal. The converter is coupled to the counter so that a count from the counter controls the voltage of a read signal from the converter. The sense circuit can stop or disable the counter upon sensing a change in conductivity in a selected memory. The count is then output as a multi-bit digital value read from the selected memory cell. In another embodiment, multiple latches are coupled to the counter, and each latch corresponds to one of multiple memory cells that a read operation reads in parallel. As the counter counts, the sense circuit triggers each latch upon sensing a change in conductivity in the corresponding memory cell. The combined outputs from different latches provide multi-bit digital data read from the memory. In still another embodiment, a shift register is coupled to shift and store counts from the counter. An old count that is selected from the shift register to compensate for sensing delay can be used as output data. In yet another embodiment, a control circuit controls a step size and a counting direction for a counter as required in a search for the count corresponding to the threshold voltage of a memory cell.
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