| 摘要 |
PCT No. PCT/JP97/01267 Sec. 371 Date May 28, 1998 Sec. 102(e) Date May 28, 1998 PCT Filed Nov. 4, 1997 PCT Pub. No. WO97/40500 PCT Pub. Date Oct. 30, 1997A semiconductor memory device of nonvolatile ferroelectric capable of stable operation without loss of logic voltage "L" data of the memory cell in rewriting operation. To achieve, for example, as shown in FIG. 1, diodes 1, 2 are connected to cell plate lines 39, 40. Therefore, in rewriting operation, if there is a parasitic resistance 3 in the cell plate line 39, it is possible to prevent occurrence of transient phenomenon of temporary transition of the cell plate line 39 to an excessive negative voltage (for example, lower than -1V) which may cause loss of data.
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