| 摘要 |
A semiconductor integrated circuit device with the SOI structure is provided, which decreases the chip area of wiring lines interconnecting p- and n-channel IGFETs, raising their integration level. This device is comprised of a semiconductor layer formed on an insulating substrate. The semiconductor layer has a first area extending along a first direction and a second area extending along the first direction. The first and second areas are adjacent to one another. A first IGFET of a first conductivity type is formed in the first area of the semiconductor layer. A second IGFET of a second conductivity type opposite to the first conductivity type is formed in the first area of the semiconductor layer. One of a pair of source/drain regions of the second IGFET is electrically connected to one of a pair of source/drain regions of the first IGFET by a first interconnection diffusion region. A third IGFET of the first conductivity type is formed in the second area of the semiconductor layer. One of a pair of source/drain regions of the third IGFET is electrically connected to one of the pair of source/drain regions of the second IGFET by a second interconnection diffusion region.
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