发明名称 SEMICONDUCTOR APPARATUS
摘要 PROBLEM TO BE SOLVED: To save defects with a small area and a large improvement effect in yield by setting the number (m) of word lines or bit lines to be replaced simultaneously by the defect relief to be an M's divisor smaller than M when a memory area is divided to M memory mats. SOLUTION: Memory mats 100-103 comprise areas 110-113 wherein normal memory cells are arranged and areas 120-123 where backup memory cells are arranged. NW×NB'/4 memory cells are arranged at intersections of NW/2 word lines W and NB/2 bit lines of the areas 110-113. L×NB/2 backup memory cells are arranged at intersections of L (L=2 in this case) spare word lines SW and NB/2 bit lines of the areas 120-123. Since the number of memory cells to be replaced simultaneously is reduced, a probability that backup memory cells replacing the normal memory cells are defective is smaller and a yield is improved.
申请公布号 JP2000076887(A) 申请公布日期 2000.03.14
申请号 JP19990204218 申请日期 1999.07.19
申请人 HITACHI LTD 发明人 HORIGUCHI SHINJI;ETO JUN;AOKI MASAKAZU;ITO KIYOO
分类号 G11C29/04;G11C11/401;G11C29/00;(IPC1-7):G11C29/00 主分类号 G11C29/04
代理机构 代理人
主权项
地址