| 摘要 |
PROBLEM TO BE SOLVED: To eliminate the need for the selection of a WL to be replaced with a redundant address, to select a redundant WL directly and to ensure the high- speed properties of an access to a memory cell. SOLUTION: The semiconductor memory has a redundant address generating circuit 2, a plurality of decoders 5A-5D decoding address data from the redundant address generating circuit 2, a plurality of latch means 8A-8D latching decoding values from a plurality of the decoders respectively, and gate circuits 10A-10D electrically conducting or interrupting the decoding values from a plurality of the decoders in response to the output signals of a plurality of the latch means.
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