| 摘要 |
PROBLEM TO BE SOLVED: To equalize load on an address line irrespective of the bit pattern of a programmed address, and to increase decoding working speed or access speed. SOLUTION: A switch circuit SW(i) corresponding to each address bit consists of a pair of CMOS transfer gates 40(i), 42(i) and one inversion circuit 44(i). The address line of a corresponding input address bit Ai is connected to the input terminal of the inversion circuit 44(i) while being joined with the N-type gate terminal of the first CMOS transfer gate 40(i) and the P-type gate terminal of the second CMOS transfer gate 42(i). The output terminal of the inversion circuit 44(i) is joined with the P-type gate terminal of the first CMOS transfer gate 40(i) and the N-type gate terminal of the second CMOS transfer gate 42(i). The node Q(i) of a corresponding fuse circuit VG(i) and the output terminal of an inversion circuit 38(i) are conjoined with the input terminals of the first and second CMOS transfer gates 40(i), 42(i) respectively.
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