发明名称 FLOATING POINT MULTIPLICATION AND ACCUMULATION UNIT
摘要 PROBLEM TO BE SOLVED: To provide a data processing system incorporated with a floating point unit for performing multiplying and accumulating operation by a small circuit. SOLUTION: In the floating point unit for performing multiplying and accumulating operation B+(A*C), a multiplier 20 determines a product (A*C) while using plural processing cycles. During the operation of the multiplier 20 and a carry preservation adder 26, an alignment shifter 34 generates an aligned value B' of an addend B. The aligned addend B' can be partially overlapped with the product (A*C) to be added. A high-order part HOP of B' not to be overlapped with the product (A*C) is connected after the output of an adder 44 for adding the product (A*C) with the overlap part of B'. When carry occurs in the addition performed by the adder 44, an incremented high-order part IHOP is connected with the output of the adder 44. This incremented high-order part IHOP is generated by the adder 44 during the processing cycle, which is not used for the other, generated by the multiplier 20 to be operated over a lot of cycles.
申请公布号 JP2000076047(A) 申请公布日期 2000.03.14
申请号 JP19990233021 申请日期 1999.08.19
申请人 ADVANCED RISC MACH LTD 发明人 DAVID VIVIEN JAGGER;DAVID TERRENCE MATHENY
分类号 G06F7/487;G06F7/485;G06F7/52;G06F7/527;G06F7/544;(IPC1-7):G06F7/52;G06F7/50 主分类号 G06F7/487
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