| 摘要 |
In an information processing system including a vector processor (132) which has a plurality of vector pipeline sets operable under control of an instruction controller (32,33) the vector pipeline sets are operable in a parallel mode or an individual mode with reference to an operation mode flag kept in a mode flag register (35). The instruction controller includes a plurality of vector instruction control units (42) which correspond to the respective vector pipeline sets and which monitor states of the vector instruction control units one another to detect whether or not an error takes place in each of the vector instruction control units. The vector pipeline sets are connected to a vector data memory (21) through a pipeline crossbar switch to fetch a common data signal from the vector data memory on demand. <IMAGE> |
