发明名称 |
DATA PROCESSING CIRCUIT WITH CACHE MEMORY |
摘要 |
The processing circuit contains a cache management unit which keeps information about a stream of addresses among addresses accessed by the processor. The cache management unit updates a current address for the stream in response to progress of execution of the program. The cache management unit makes selected storage locations in the cache memory available for reuse, a storage location in the cache memory which is in use for the data corresponding to the particular address being made available for reuse dependent on a position of the particular address relative to the current address. |
申请公布号 |
WO9959070(A3) |
申请公布日期 |
2000.03.09 |
申请号 |
WO1999IB00785 |
申请日期 |
1999.04.29 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V.;PHILIPS AB |
发明人 |
VAN DER WOLF, PIETER;STRUIK, PIETER |
分类号 |
G06F12/08;G06F12/12 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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