发明名称 |
4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation |
摘要 |
A densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, acting as a channel, formed between source and drain regions. The source regions are self-aligned and located below the pillars. The source regions of adjacent bitlines are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F2 to be maintained. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. The source may be initially implanted. Alternatively, the source may be diffused below the pillars after forming thereof. In this case, the source diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
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申请公布号 |
US6033957(A) |
申请公布日期 |
2000.03.07 |
申请号 |
US19970960247 |
申请日期 |
1997.10.29 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BURNS, JR., STUART MCALLISTER;HANAFI, HUSSEIN IBRAHIM;WELSER, JEFFREY J.;KOCON, WALDEMAR WALTER |
分类号 |
H01L21/8242;H01L21/8247;H01L27/108;H01L27/115;H01L29/423;H01L29/78;H01L29/788;H01L29/792;(IPC1-7):H01L21/336;H01L21/823 |
主分类号 |
H01L21/8242 |
代理机构 |
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地址 |
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