发明名称 |
Interconnect structure for protecting a transistor gate from charge damage |
摘要 |
A method and apparatus for preventing charge damage to a protected structure during processing of a semiconductor device. A first source/drain region of a protection transistor is coupled to a protected transistor gate. A second source/drain region of the protection transistor is coupled to ground. The protection transistor is then turned on during the processing of the device to ground the protected transistor gate.
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申请公布号 |
US6034433(A) |
申请公布日期 |
2000.03.07 |
申请号 |
US19970997502 |
申请日期 |
1997.12.23 |
申请人 |
INTEL CORPORATION |
发明人 |
BEATTY, TIMOTHY S. |
分类号 |
H01L23/60;(IPC1-7):H01L23/48;H01L23/52;H01L23/62 |
主分类号 |
H01L23/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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