Microprocessor with reduced power consumption in accordance with usage condition

摘要

A microprocessor that includes a processor (6) for executing an instruction in accordance with an internal clock signal, an instructing section (3) for outputting a frequency multiplication rate instructing signal corresponding to the data output from the processor, and a data selecting section (2) for selectively outputting the frequency multiplication rate instructing signal. A PLL section changes the frequency of the internal clock signal in response to the frequency multiplication rate instructing signal output from the data selecting section. Inhibiting section inhibits the internal clock signal from being supplied from a PLL section to the processor for a predetermined period until the frequency of the internal clock signal in the PLL section becomes stable.