Semiconductor device having a reduced height floating gate

摘要

Arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates by advantageously reducing the height of the floating gates in particular locations. The reduced height floating gate's topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.