Integrated circuit

摘要

PCT No. PCT/GB96/00295 Sec. 371 Date Feb. 19, 1998 Sec. 102(e) Date Feb. 19, 1998 PCT Filed Feb. 12, 1996 PCT Pub. No. WO96/25720 PCT Pub. Date Aug. 22, 1996A single chip processor for use in a smart card has a plurality of instruction memory areas and a processor. Different instructions sets are selectively executable in response to a signal defining a memory area from which instructions are supplied. Preferably instruction and data memory areas are addressable as pages, wherein a page address cannot be directly accessed by a subset of instructions. The processor may include a central processing unit and a cryptographic logic unit which operate at different times and share common instruction memory and sequencing logic. Instructions are supplied to said cryptographic logic unit at an integer multiple of the rate at which they are supplied to said central processing unit.