HYBRID SEMICONDUCTOR DEVICE HAVING A MEMORY AND A LOGIC AND A HOLD TIME CONTROL METHOD

摘要

PURPOSE: A hybrid semiconductor device composed of a memory and a logic is provided to reduce transition current of data inputted to the memory while securing enough margin of data hold time. CONSTITUTION: The hybrid semiconductor device comprising a logic, a memory and data bus for electrically connecting them which operates in synchronism with an external clock signal supplied from the exterior, further comprises: a rising delay circuit for delaying a rising edge of the external clock signal; a falling delay circuit for delaying a falling edge of the external clock signal; a first switching circuit for receiving data outputted from the logic and outputting the data in response to an output of the falling delay circuit; a first latch circuit for storing the data output from the first switching circuit; a second switching circuit for receiving data outputted from the first latch circuit and outputting the data in response to an output of the rising delay edge; and a second latch circuit for storing the data output from the second switching circuit, a data output from the second latch circuit being transmitted through the data bus to the memory.