发明名称 SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE USING THE SAME
摘要 PROBLEM TO BE SOLVED: To increase effective area of solder bump arrangement. SOLUTION: Electrode contacting openings 17 are opened on a shielding film 16, that coats the main surface of an active region 11 side of a semiconductor chip 10, solder bumps 12 are protruded at positions apart from the electrode contacting openings 17, and the solder bumps 12 are electrically connected to the electrode connecting openings 17 with electrical wiring 18 laid on the surface of the shielding film 16. Height h of the solder bumps 12, distance L between the edge of a solder bump 12 and an electrode connecting opening 17, opening width a of the electrode connecting opening 17, and thickness t of the shielding film are designed so as to satisfy the inequality (h/L)<(t/a). As a result of this, since the failure of a memory cell due to &alpha;-ray infiltrating from an electrode connecting opening can be prevented, because the &alpha;-ray from the solder bump inside can be prevented from being introduced into the inside of the chip. In a C4 mounting structure of a memory chip, since the latitude in solder bump layout can be increased, memory chip or the area of a semiconductor device using the same can be reduced.
申请公布号 JP2000068313(A) 申请公布日期 2000.03.03
申请号 JP19980246523 申请日期 1998.08.18
申请人 HITACHI LTD 发明人 ANDO HIDEKO;KIKUCHI HIROSHI;YOSHIDA IKUO;SATO TOSHIHIKO
分类号 H01L21/60 主分类号 H01L21/60
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