| 摘要 |
PROBLEM TO BE SOLVED: To provide a phase synchronization technology that has already generated clocks synchronously with each other before resetting is released. SOLUTION: A frequency divider 17 of a master chip 101 frequency-divides a clock CK to generate a frequency division clock 33 and a frequency divider 27 of a slave chip 201 frequency-divides the clock CK to generate a frequency division clock 43. The frequency divider 17 outputs a carry signal CY to its own reset terminal R via a tri-state buffer 13 and outputs the carry signal CY to a reset terminal R of the frequency divider 27 via tri-state buffers 13, 14, input output ports 31, 41 and a tri-state buffer 25 in this order respectively. Since the carry signal CY is activated in an internal state before one period of the clock CK earlier than an internal state reset by the frequency divider 17 both the frequency dividers 17, 27 are reset with the carry signal CY without losing a ratio of frequency division of the frequency dividers 17, 27. |
