发明名称 DEVICE AND METHOD FOR HIGH-SPEED IMPROVED DISCRETE COSINE TRANSFORMATION
摘要 <p>PROBLEM TO BE SOLVED: To remarkably reduce the capacitance of a ROM required for an instruction and to easily make a dedicated LSI or the like into hardware by making an arithmetic part common for respective kinds of butterfly operation of different types into module and setting a loop variable for reflectively calling the arithmetic module. SOLUTION: Concerning the butterfly operation to be performed over plural stages, this device is provided with a means for making arithmetic processing common for each type of different butterfly forms, determining the loop variable with a degree and the number of stages as functions and setting the loop variable for executing arithmetic processing and a means for setting an address to a first storage means 600 based on the loop variable. Arithmetic processing means 605 and 606 perform processing for mutually adding/subtracting coefficients in the first storage means 600 corresponding to the type of number of stages of the butterfly operation and performs adding/subtracting processing after multiplying this coefficient with a cosine or sine value stored in a second storage means 602.</p>
申请公布号 JP2000067032(A) 申请公布日期 2000.03.03
申请号 JP19980235168 申请日期 1998.08.21
申请人 NEC CORP 发明人 MATSUO HIROSHI
分类号 G06F17/14;(IPC1-7):G06F17/14 主分类号 G06F17/14
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