| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the number (n) of transistors being connected in series and each deciding a resistance value in a current path and the number (m) of bank selecting lines per bit contact by changing constitution of a memory cell array in a NOR type cell for mask ROM. SOLUTION: In a memory cell for a mask ROM in which four sub-bit lines are connected to a main bit line DGi and virtual ground lines VGi, VGi+1 through one contact and four bank selection transistors, respective sub-bit lines are connected to three bank selecting lines, while two virtual ground lines VGi, VGi+1 are arranged in parallel at right and left sides of the main bit line DGi, a memory cell transistor is selected based on signal levels of the bank selecting line and the virtual ground lines VGi, VGi+1.</p> |
