发明名称 SYNCHRONIZATION LATCH DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a synchronization latch circuit that corrects a frame timing based on a value stored in a memory (correction history information when a unique word UW pattern is detected) even when the UW pattern cannot be detected. SOLUTION: The time when a UW pattern is to be detected in advance is used for a UW pattern detection reference value 109 (the time when a receiver detects a UW pattern in the case that no frame timing is deviated between a transmitter and the receiver) in a frame timing of the receiver and a difference between the reference value 109 and a value 108 of a reference timer that is latched through detection of the UW pattern is calculated and the frame timing is corrected based on a timing deviation 111. In this case, the calculated difference 111 is stored in a memory 112. Thus, even when no UW pattern is detected, the frame timing is corrected based on the value stored in the memory 112 (correction history information when the UW pattern is detected).
申请公布号 JP2000068994(A) 申请公布日期 2000.03.03
申请号 JP19980249074 申请日期 1998.08.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHINODA KAZUO
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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