发明名称 CELL LAYOUT, LAYOUT METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To increase the number of systems for power supply wiring inside the same block and to reduce an area by the effective utilization of multilayer wiring. SOLUTION: A layout is made by using a standard cell library and wiring elements for power supply to a cell is present only in the inside of a cell outer frame 18. Thus, power supply wiring connection between the cell will not be conducted only by the completion of the arrangement process of the cells, but the power supply wiring is connected for the first time in a wiring process, and connection to the power supply systems of different potentials is conducted for respective cells. Also by using the wiring layer of a highest layer to the source region of a transistor or a region for a base potential connection as the wiring element of the power supply wiring inside the cell and connecting the transistor or a base from there by a stacked via, a region capable of using the wiring of a lower layer for signal wiring is widened and reduction of the region as the block is realized.
申请公布号 JP2000068382(A) 申请公布日期 2000.03.03
申请号 JP19980237149 申请日期 1998.08.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMADA AKIHIRO
分类号 H01L21/82;(IPC1-7):H01L21/82 主分类号 H01L21/82
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