发明名称 PEAK DETECTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide the peak detection circuit where low power consumption, a high input impedance a low output impedance and reduction in number of components are realized and that detects a peak level of an input signal even when the level of the input signal is low. SOLUTION: Transistors(TRs) Q1 and Q2 in diode connection connect with each other in series between two current sources I1, I2 of this peak detection circuit and a capacitor C1 (C2) that detects a ±peak of an input signal Vin connects in parallel with the current source I1 (I2). Furthermore, the peak detection circuit is provided with an output level shifter (buffer) consisting of a TR Q3 and a current source 13 and with an output level shifter (buffer) consisting of a TR Q4 and a current source 14.
申请公布号 JP2000068802(A) 申请公布日期 2000.03.03
申请号 JP19980240581 申请日期 1998.08.26
申请人 ASAHI KASEI MICROSYSTEMS KK 发明人 IKEDA MASAKI
分类号 H03K5/1532 主分类号 H03K5/1532
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