发明名称 |
PLL CONTROLLER, PLL CONTROL METHOD AND LIMITER |
摘要 |
PROBLEM TO BE SOLVED: To prevent the occurrence of a temporary stop of an output of a voltage controlled oscillator due to a rapid change in a level of a control signal given to the voltage controlled oscillator with respect to the control method for a phase locked loop PLL in a transmitter such as a MODEM. SOLUTION: The output terminal of a PLL section 24 is provided with a limiter 29 that limits an output level of the PLL section 24 and an output of the limiter 29 is given to a voltage controlled oscillator VCXO 27. The limiter 29 obtains a difference between its input signal and its output signal and limits a change in an output of the limiter 29 to a limit value when the difference exceeds a predetermined limit. The limier 29 uses an output change for the difference when the difference does not exceed the limit. |
申请公布号 |
JP2000068824(A) |
申请公布日期 |
2000.03.03 |
申请号 |
JP19980235185 |
申请日期 |
1998.08.21 |
申请人 |
FUJITSU LTD |
发明人 |
KAWADA NOBORU;KAKO TAKASHI;ASAHINA TAKESHI;OGAWA TORU;MIYAZAWA HIDEO |
分类号 |
H03L7/08;H03L7/091;H03L7/093;H04L7/033 |
主分类号 |
H03L7/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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