发明名称 MEMORY CONTROLLER
摘要 PROBLEM TO BE SOLVED: To improve access efficiency by making data from bas masters writable in a memory in a page mode by providing a memory access sequencer having a specified function. SOLUTION: A memory access sequencer 5 has a function which compares addresses (c) to (f) from bus masters 2 and 3 and write data holding parts 10 and 11 with an address (g) at the time of the preceding memory access and preferentially selects a writeback request on the same page. The sequencer 5 selects the request of an address to be a page mode among the low addresses (c) and (d) of writeback requests (h) and (j) from the bas masters 2 and 3 and the row addresses (e) and (f) of the write data holding parts 10 and 11 and performs memory write to a memory element part 14. At the same time, it updates the low address (g) at the time of memory access held by an address latch 12. A flag 22 showing the existence of the address of the row address (g) is set in the address latch 12.
申请公布号 JP2000066946(A) 申请公布日期 2000.03.03
申请号 JP19980230966 申请日期 1998.08.17
申请人 NEC CORP 发明人 OGAWA TAKASHI
分类号 G06F12/00;G06F12/02;G06F13/16;(IPC1-7):G06F12/00 主分类号 G06F12/00
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