| 摘要 |
PROBLEM TO BE SOLVED: To obtain an I/O log recording circuit capable of preventing the performance of a CPU from being reduced without providing a main memory with an exclusive area for recording an I/O log. SOLUTION: An I/O memory control circuit 4 recognizes an I/O cycle or not, based on a signal from a CPU 1, and at the time of recognizing the I/O memory, generates three write timing in an I/O log storing memory 7 during the I/O cycle. A date is written in the memory 7 at the 1st write timing and an address and data are respectively written at the 2nd and 3rd writing timing. The selection of date/address/data is executed by a selection signal outputted from the circuit 4 to a selector 5 and an address for the memory 7 is generated by the circuit 4. After the end of three writing, the circuit 4 allows the CPU 1 to end the I/O cycle.
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