发明名称 SEMICONDUCTOR MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To provide a semiconductor memory which surely prevents erroneous write without complicating the internal constitution. SOLUTION: This semiconductor memory has a memory cell array 2 of a virtual ground method, first to third source line selection transistors Qs11 to Qs1n, Qs21 to Qs2n, Qs31 to Qs3n and first to third drain line selection transistors Qd11 to Qd1n, Qd21 to Qd2n, Qd31 to Qd3n. One source line of adjacent two source lines is connected to second and third source line selection transistors, and either of the transistors is surely turned 'on'. One drain line of adjacent two drain lines is connected to the second and third drain line selection transistors, and either of the transistors is surely turned 'on'. For this reason, a source line and a drain line with not be in floating states, even when data is written in any of memory cells.</p>
申请公布号 JP2000068485(A) 申请公布日期 2000.03.03
申请号 JP19980239050 申请日期 1998.08.25
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 KURATA MINORU;TATSUMI YUICHI
分类号 G11C16/02;G11C16/04;G11C16/06;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L27/115;H01L21/824 主分类号 G11C16/02
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