Reconfigurable gate array cells for automatic engineering change order

摘要

A method and system to efficiently incorporate engineering change order (ECO) modifications into an integrated circuit layout having configurable gate array cells is provided. In generating the original integrated circuit layout, extra gate array cells are inserted into the layout. These gate array cells can be reconfigured to modify their functionality according to changes specified by the ECO. A new netlist with a description of the required modifications is generated and provided to a place-and-route CAD tool to create a new layout of the integrated circuit.