| 摘要 |
A data processor testing apparatus, in which, in an access instruction executing section, an instruction string to be tested for access to cache memories as an object for execution is previously prepared, access data on a memory is set in an instruction cache memory and operand cache memory according to the instruction string to be tested, and in a BI control section, the access data set as described above is invalidated with the BI signal when the access data set in the operand cache memory is data for an address previously decided as an object for invalidation on the memory, and determination is made by a comparison control section as to whether a result of invalidation is acceptable or not.
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