Flattening process for epitaxial semiconductor wafers

摘要

Process for the preparation of an epitaxial wafer having a total thickness variation and/or site total indicated reading of less than about 1.0 mu ms. The distance between the front and back surfaces of the epitaxial wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the epitaxial wafer in a stock removal step to reduce the thickness of the epitaxial wafer to the target thickness, Tt, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and Tt.