发明名称 |
Method for producing a multilayer interconnection structure |
摘要 |
An apparatus and method for forming solder interconnection structures that reduce thermo-mechanical stresses at the solder joints of a semiconductor device and its supporting substrate. In one embodiment, the solder interconnection structure of the present invention comprises a semiconductor device and a substrate having a plurality of solder connections extending from the substrate to electrodes or bond pads on the semiconductor device. A multilayer structure is disposed between the semiconductor device and substrate filling the gap formed by the solder connections. The multilayer structure includes a first layer and a second layer, each having a different coefficient of thermal expansion. Thus, in accordance with the present invention, the stress concentration points are moved away from the solder joints of the semiconductor device and substrate to a point located between the first and second layers of the filler structure. |
申请公布号 |
US6030854(A) |
申请公布日期 |
2000.02.29 |
申请号 |
US19980111268 |
申请日期 |
1998.07.06 |
申请人 |
INTEL CORPORATION |
发明人 |
MASHIMOTO, YOHKO;INOUE, SHUJI;KUBOTA, JIRO;KURODA, MASHAHIRO |
分类号 |
H01L21/56;H01L21/60;(IPC1-7):H01L23/48 |
主分类号 |
H01L21/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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