Clock waveform synthesizer

摘要

A clock waveform synthesizer that will create a timing signal that is a multiple of the frequency of an master clock is disclosed and has the capability to programmably adjust the rising edges and falling edges of the synthesized waveform within the period of the master clocks. The clock waveform synthesizer has a multi-tapped delay line. The multi-tapped delay line will create replications of the master clock that are incrementally delayed from the master clock to create a plurality of delay signals. A fraction of the plurality of delay signals will be the inputs to each of a plurality of multiplexers. A select port on each of the multiplexers will receive a select signal to choose one delay signal of the fraction of the plurality of delay signals. The one selected delay signals will be the input to the set terminals and reset terminals of a plurality of edge-triggered set/reset flip-flops. The edge-triggered set/reset flip-flop has an output terminal which will transit from a first logic level to a second logic level when the one selected delay signals is received at the set terminal and will transit from the second logic level to the first logic level when the one selected delay signal is received at the reset terminal. The outputs of the plurality of edge-triggered set/reset flip-flops are connected to the inputs of a combining logic gate, which will combine the signals at the outputs of the edge-triggered set/reset flip-flops to form the synthesized timing signal.