| 摘要 |
A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, or in logic circuits, is disclosed. In one embodiment, a plurality of postcharged speed-up circuits, each having a single network node, is connected to the intermediate nodes of a programmable interconnect architecture. Each speed-up circuit monitors the logic level on the network node. When a circuit detects a substantial change in logic level, away from the stand-by level, it temporarily enforces that change by connecting its network node to the signaling logic level. Thus, on each node, a low-impedance enhancement of the signal driving the node temporarily appears. This causes the potential on neighboring nodes, connected through conducting programmable switches, to change towards the signaling level, and their speed-up circuits in turn temporarily enforce the new level. After the temporary enforcement of the signaling level, each speed-up circuit forces its network node back to the stand-by level, for a predetermined period of time. Thus, a forced pulse away from the stand-by logic level towards the signaling level on a node quickly propagates to its connected nodes.
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