| 摘要 |
A refresh circuitry is coupled to memory cell array (212) to perform freshness evaluation cycles within time period equal to or less than data retention time of memory cells. A current freshness evaluation cycle uses one history bit to determine if refresh of one memory cell is to occur in response to current freshness evaluation cycle of to be postponed until later evaluation cycle. The device has a number of memory cells which are configured into memory rows. Each row contains a unique set to memory cells selected from several history bits which track refresh history for each memory row. The rows are arranged into a number of refresh groups. One history bit is maintained for each refresh group. The groups define memory tiles and the tiles are grouped into memory banks. The history bit is a logic value stored in a volatile static random access storage element. An Independent claim is also included for memory refreshing method. |
