| 摘要 |
PROBLEM TO BE SOLVED: To enable phase adjusting operation in a short time by providing a DLL(delay locked loop) circuit for executing phase adjustment in accordance with an output load. SOLUTION: This DLL circuit is provided with a first variable delay circuit 14 for inputting a reference clock CLK 11 and outputing a clock delayed by a controlled delay time a second variable delay circuit 20 for inputting the output of the circuit 14 and outputting the clock delayed by a prescribed delay time, and phase comparing and delay-control circuits 15 and 16 for comparing the phases the clock CLK 11 and a delay clock d-i-CLK and controlling the delay quantity of the first variable delay circuit so that these phases are matched with each other. The operation delaying time of an output buffer different in accordance with an external load is measured to adjust the delay quantity of the second variable delay circuit in the feedback loop of the DLL circuit based on the operation delay time. |
