| 摘要 |
PROBLEM TO BE SOLVED: To provide a digital converting circuit capable of drastically reducing the storage capacity for the same conversion characteristics without remarkably inceasing the storage capacity of a storage circuit even when the number of bits of an address line is increased and being used for a gamma correcting circuit. SOLUTION: This circuit is provided with an AND gate 102 which separates an input digital signal to the high-order and low-order bits, stores a RAM module 100 with a converted digital signal corresponding to the high-order bits and a correction value for the converted digital signal as data, and selects a converted digital signal correction value between a converted digital signal read out when the high-order bits are inputted as an address to the RAM module 100 and the converted digital signal correction value with the low-order one bit of the input digital signal and an adder 101 which adds the output of the AND gate 102 the converted digital signal, and the output of this adder 101 is regarded as the output of the digital converting circuit. |
