| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a delay circuit for reducing the fluctuation of delay time by power supply voltage fluctuation. SOLUTION: In this delay circuit, at the time of defining the threshold voltage of p-ch transistors TR3 and TR4 as Vtp, a voltage VGS between the gate and source of transistors TR9-TR12 becomes 2Vtp when a power supply voltage is high. Thus for the transistors TR9-TR12, when the power supply voltage Vcc is high, driving force is smaller than before. As a result, for inverters 1-4, even when the power supply voltage Vcc rises, the change (reduction) of the delay time is less than before.</p> |
