发明名称 SEMICONDUCTOR MEMORY DEVICE WITH TRUE/COMPLEMENT REDUNDANT STRUCTURE
摘要 PROBLEM TO BE SOLVED: To increase redundant operation speed by providing a plurality of memory cells being arranged so that the memory cells correspond to a plurality of memory blocks, by providing a plurality of block sensing amplifiers being arranged so that the block sensing amplifiers correspond to a plurality of memory blocks, and by generating a sensing amplification control signal, a column selection signal, and a row selection signal when a selected row is defective. SOLUTION: Block sensing amplification circuits BSA1-BSAn sense and amplify information in a memory block where a corresponding block sensing amplification circuit is selected when one of the block sensing amplification circuits is selected. The read/write operation of information to the memory cell of an arbitrary row in a memory block BLK1 is performed, a main word line that is related to a defective memory cell is selected by a column decoder 130, and one of the main word line and a selected sub word line is selected by SWD: 120. The row of the defective memory cell is replaced by a redundant row by a selection signal from a redundant controller 200.
申请公布号 JP2000057796(A) 申请公布日期 2000.02.25
申请号 JP19990228625 申请日期 1999.08.12
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 CHO TETSUMIN;TEI MINCHURU
分类号 G11C29/04;G11C29/00;(IPC1-7):G11C29/00 主分类号 G11C29/04
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