发明名称 METHOD FOR DESIGNING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To mitigate the restriction violation of a constraint violation path, to prevent the deterioration of a wiring jam after arrangement, and moreover, to obtain a wiring length being more close to an actual wiring processing and wiring jam information. SOLUTION: A cell arrangement processing part 12 executes the arrangement processing of a cell based on inputted information. An arrangement analysis processing part 13 executes the prediction processing of a wiring jam degree and a virtual wiring length against the arrangement result of the cell, which is executed in the cell arrangement processing part 12, compares the result of the virtual wiring length with previously inputted constraint information and retrieves the path with a timing constraint violation. The cell on the path with the timing constraint violation is returned to the cell arrangement processing part 12 together with wiring jam degree information by obtaining re-arrangement information and re-arrangement is executed based on re-arrangement information. Arrangement analysis is executed again concerning arrangement information after re-arrangement. When a judgement result is OK, the wiring processing is executed in a wiring processing part 14.
申请公布号 JP2000057178(A) 申请公布日期 2000.02.25
申请号 JP19980227346 申请日期 1998.08.11
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 SATO MACHIKO
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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