| 摘要 |
PROBLEM TO BE SOLVED: To provide the bus conflict preventing circuit which prevents unnecessary data from being sent out of other tri-state buffers which have failed to acquire the bus right because of slight time differences after access to the tri-state buffer having acquired the bus right at the earliest is completed. SOLUTION: The tri-state buffers 10a, 10b, and 10c are supplied with corresponding enable signals EN1, EN2, and EN3. Enable signal control circuits of the tri-state buffers 10a, 10b, and 10c are provided with AND gates 20a, 20b, and 20c and, for example, the AND gates 20a, 20b and 20c output AND results between their enable signals and the inverse of other outputs to control the respective tri-state buffers so that the enable signal EN1 and the inverse of the outputs of other AND gates 20b and 20c are inputted to the AND gate 20a, and its AND is outputted to the tri-state buffer 10a. Consequently, the gate having accessed the enable signal at the earliest drives the tri-state buffer and masks gates gaining access later so that a bus conflict is prevented.
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