发明名称 KEY SCHEDULE APPARATUS FOR DES
摘要 PROBLEM TO BE SOLVED: To make it possible to speed up a key schedule in spite of a small circuit scale by providing the apparatus with latch circuits for holding key data before forming the magnification keys to be supplied to respective stages and forming the magnification keys of the respective stages by the key data held in the latch circuits. SOLUTION: The key data subjected to prescribed PC1 reduction type transposition with a PC1 transposer 1 is selected by a selector 2 and is latched by a flip-flop 3 and is then subjected to prescribed PC2 reduction type transposition with a PC2 transposer 8, by which the magnification key 1 of the first stage is formed. The output of the flip-flop 3 is subjected to prescribed shift processing in respective shifters 4, 5, 6 and is further subjected to the prescribed PC2 reduction type transposition by respective PC2 transposers 9 to 11, by which the magnification keys 2 to 4 of the second to the fourth stage are formed. In the next cycle, the key data fed back from the final stage of the previous time is selected by the selector 2 and the magnification keys 1 to 4 of the fifth to the 8th stage are similarly formed.
申请公布号 JP2000056679(A) 申请公布日期 2000.02.25
申请号 JP19980227405 申请日期 1998.08.11
申请人 FUJITSU LTD 发明人 OKADA SOICHI;HASEBE TAKAYUKI
分类号 G09C1/00;H04L9/06;(IPC1-7):G09C1/00 主分类号 G09C1/00
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