发明名称 START-STOP SYNCHRONOUS DATA TRANSMISSION/RECEPTION METHOD
摘要 <p>PROBLEM TO BE SOLVED: To surely receive data from a data transmitter side in response to a revision of a data transmission rate, even when the data transmission rate is revised on the way to data transmission or reception. SOLUTION: Since the bit period of start bits is detected, based on a bit time width measurement of a start bit '0' with a trailing detection pulse 13 and a leading detection pulse 12 from a start bit detection circuit 21 to a counter 22 at a data receiver side receiving start bits '0', '1' from a data transmitter side, data from the start bit '1' to a stop bit '1' are surely received sequentially in bit units.</p>
申请公布号 JP2000059446(A) 申请公布日期 2000.02.25
申请号 JP19980227124 申请日期 1998.08.11
申请人 HITACHI COMMUN SYST INC 发明人 FURUKAWA YOSHIAKI
分类号 H04L25/38;H04L7/04;H04L29/08;(IPC1-7):H04L25/38 主分类号 H04L25/38
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