PLL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCORPORATED WITH PLL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To prevent an FF circuit from being erroneously operated by adjusting the duty of a clock signal to be supplied for the FF circuit of an individual circuit block. SOLUTION: The output signal 111a of a delay circuit 21 is outputted by being delayed by a prescribed time from the output signal 111 of an inverter(INV) 11 through a delay control circuit 22 by the instruction from outside. An arithmetic circuit 23 executes the AND operation of the output signal 115 of an inverter(INV) 15 and outputs a second clock signal 117 of a duty different from that of a first clock signal 116 outputted from a buffer circuit 19.