| 摘要 |
PROBLEM TO BE SOLVED: To keep stability of a clock recovery circuit and to reduce a synchronization time till generation of an internal clock by dividing a 1st reference clock to one input node of plural 2nd delay circuits and delivering it to a final stage. SOLUTION: A clock recovery circuit consists of a rough adjustment clock recovery circuit CTC including a control circuit MCC and a fine adjustment clock recovery circuit FTC. A clock given from a delay monitor DMC to a traveling direction delay circuit FDA in the rough adjustment clock recovery circuit CTC is delayed by a prescribed amount of delay every time the clock passes through each delay circuit and plural output terminals (NF0-NFm) output plural delayed clock signals whose delay times are arithmetically number. Furthermore, each of arbiters ARB0-ARBm in the control circuit MCC compares phases of the clock signals received from 1st and 2nd inputs and provides an output according to the prescribed phase condition. |
