WAFER-LEVEL BURN-IN PROCESS AND TEST

摘要

PURPOSE: A wafer-level burn-in process and test is provided, which identifies a known good die to perform a semiconductor device in a wafer level. CONSTITUTION: The apparatus for wafer-level burn-in process and test comprises: test substrates (106, 108) for having active electronic components such as ASICs (106) mounted to an interconnection substrate or incorporated therein; a metallic spring contact element (110) for effecting interconnections between the ASICs (106); and a plurality of devices-under-test (DUTs) to be located on a wafer-under-test (WUT)(102), wherein test substrates (106, 108), the metallic spring contact element (110) and DUTs are all disposed in a vacuum vessel so that the ASICs (106) and can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. Thereby, it is possible to mount the precise alignment of a plurality of ASICs on the support substrate.