发明名称 DESIGN METHOD AND DESIGN EQUIPMENT OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To prevent increase in wiring capacitance by judging whether a flattened pattern can be arranged in positions of all through holes, arranging the flattened pattern in the position capable of arrangement according to the judgment, and registering the final arrangement coordinate of the flattened pattern. SOLUTION: An arrangement judging part 8 of a program processing part 5 judges whether a flattened pattern can be arranged in the positions of all through holes, according to the rule of a wiring condition file 3, in the order of priority of a layout position file 2. When the flattened pattern can not be arranged by the judging process, a pattern layout part 9 judges whether the flattened pattern can be arranged in the next position, and the flattened part is arranged in the position capable of layout. A coordinate registering part 10 executes sequentially the layout to the positions of all through holes, and registers the final layout coordinate of the flattened pattern in design data base.
申请公布号 JP2000058657(A) 申请公布日期 2000.02.25
申请号 JP19980222519 申请日期 1998.08.06
申请人 HITACHI LTD;HITACHI INFORMATION TECHNOLOGY CO LTD 发明人 MOTOYOSHI MINORU;ASANUMA TOSHIFUMI
分类号 H01L21/3205;G06F17/50;H01L21/82;(IPC1-7):H01L21/82;H01L21/320 主分类号 H01L21/3205
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