发明名称 MULTIPLICATION DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce the hardware quantity of a multiplication device which divides the multi plier of n-bits into M bits and outputs a final multiplication result by executing multiplication for M-times in a multiplication device which divides multiplier n-bits into plural pieces of bits at the time of multiplying the multiplier of n-bits and a multiplicand, executes multiplica tion plural times and outputs the final multiplication result. SOLUTION: A multiplication device for dividing multiplier n-bits into M bits at the time of multiplying a binary multiplicand of n-bits and a binary multiplier of n-bits, executing the multiplication, of n-bits and n/M bits for M-times and obtaining a multiplication result is provided with a multiplier selection means 2 which sequentially selects the multipliers for M-times by every number of bits equal to the integer part of a quotient n/M from the low-order when the quotient n/M has a remainder '1', a multiplicand selection means 4 which sequentially selects only the number of bits, which is obtained by adding '1' to the integer part of n/M for the first time and only the number of bits, which is equal to the integer part of n/M from the second time to M-th times in the multiplication of the multiplicand for M-times from the low-order bit side of the multiplicand and a multiplication means 7 adding the output of the multiplicand selection means 4 to the high-order part of a product obtd. by multiplying the n-bits of the multiplicand 3 by the output of the multiplier selection means 2 and obtaining a partial multiplication result in respective times.
申请公布号 JP2000056950(A) 申请公布日期 2000.02.25
申请号 JP19990244072 申请日期 1999.08.30
申请人 FUJITSU LTD 发明人 KOBAYAKAWA KAZUE
分类号 G06F7/53;G06F7/508;G06F7/52;G06F7/527;(IPC1-7):G06F7/52 主分类号 G06F7/53
代理机构 代理人
主权项
地址