发明名称 FORMATION OF INTEGRATED CIRCUIT WIRING
摘要 PROBLEM TO BE SOLVED: To suppress the occurrence of leak currents by a redeposited wiring metal by providing a resist pattern by combining each-layer wiring pattern of multilayered wiring formed, by alternately laminating insulating films and wiring upon another on a substrate with each other and removing resist patterns by vertically dry-etching the insulating films by using the resist pattern as a mask. SOLUTION: A photoresist pattern 4 is formed by laminating the wiring pattern of each layer upon another on formed three-layer wiring. Insulating films 2 among wires are vertically etched by reactive ion etching(RIE) by using the pattern 4 as a mask. When the pattern 4 is removed, the insulating films 2 among wires are removed and such a wiring structure that wiring 3 is supported by platy insulators 5 is left. Therefore, the wiring metal is not directly sputtered by the RIE nor redeposits and forms leak current paths. In addition, the parasitic capacitance of the multilayered wiring 3 can be reduced by removing the insulating films beside the wiring by covering the wiring with a resist and narrowing the insulating films on and under the wiring 3 in holdable states.
申请公布号 JP2000058549(A) 申请公布日期 2000.02.25
申请号 JP19980220339 申请日期 1998.08.04
申请人 NEC CORP 发明人 ASAI SHUJI
分类号 H01L21/3213;H01L21/768;H01L23/522;(IPC1-7):H01L21/321 主分类号 H01L21/3213
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