发明名称 4-2 COMPRESSOR CIRCUIT AND MULTIPLIER
摘要 PROBLEM TO BE SOLVED: To provide a 4-2 compressor circuit and a multiplier, which can add four inputs and the quinary of a first carry from the low-order bit side, calculates the first and second carries that are generated as a result with a simple circuit constitution and can calculate the values at a high speed. SOLUTION: When a value supplied through an input terminal IN3H whose decision time is fast is '0', and a value supplied through an input terminal IN4H whose decision time is fast is '1', the values of inputs supplied through input terminals IN3H and IN3L and input terminals IN4H and IN4L are inverted and the combination number of four input values is reduced.
申请公布号 JP2000056949(A) 申请公布日期 2000.02.25
申请号 JP19980226144 申请日期 1998.08.10
申请人 MITSUBISHI ELECTRIC CORP 发明人 HIRASE YUKO;SAWAI KATSUNORI
分类号 G06F7/509;G06F7/52;G06F7/523;G06F7/53;G06F7/60 主分类号 G06F7/509
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