发明名称 Variable delaying circuit
摘要 A first capacitor 7, a resistor 5, and a second capacitor 6 are connected in series between an output node A and a first power supply line 22. In addition, a first switch 8 is connected between the connected point of the first capacitor 7 and the resistor 5 and a second power supply line. A second switch 9 is connected in parallel with the second capacitor 6. The first and second switches 8 and 9 are opened or closed corresponding to the level of the input signal. <IMAGE>
申请公布号 EP0831586(A3) 申请公布日期 2000.02.23
申请号 EP19970115624 申请日期 1997.09.09
申请人 NEC CORPORATION 发明人 WATARAI, SEIICHI
分类号 H03K5/13;H03K5/131 主分类号 H03K5/13
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