发明名称 |
Arbitration circuit for arbitrating requests from multiple processors |
摘要 |
A round robin arbitration circuit arbitrating N requests has a register storing one of N values, a priority encoder selecting one of N priority patterns according to the value in the register and assigning priorities to the requests based on the selected priority pattern, thereby conducting arbitration between the requests, a circuit updating the value in the register among the N values in a predetermined order synchronously with the arbitration, and a circuit updating the value in the register among the N values in the predetermined order at regular intervals that are asynchronous with the arbitration. At the regular intervals that are asynchronous with the arbitration, a jump is made in the predetermined updating order of the values to be set in the register. Accordingly, even if live-lock occurs, it will be solved when such a jump is made to make the number of priority patterns disagree with the number of requests issued in a loop.
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申请公布号 |
US6029219(A) |
申请公布日期 |
2000.02.22 |
申请号 |
US19980030279 |
申请日期 |
1998.02.25 |
申请人 |
FUJITSU LIMITED |
发明人 |
MICHIZONO, MASATOSHI;MUTA, TOSHIYUKI;ODAHARA, KOICHI;SAKURAI, YASUTOMO;KATOH, SHINYA |
分类号 |
G06F15/16;G06F13/362;G06F15/167;G06F15/177;(IPC1-7):G06F13/14 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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